Physics Drives Physical into the Mainstream - New demands on design tools

You’ve finished the RTL for your FPGA design. You’re targeting the latest SRAM FPGA family and using the works: embedded soft-core processor, internal memory with external RAM interfaces, a DSP datapath leveraging built-in hardwired multipliers, and the FPGA vendor’s PCI core. After weeks of architectural and RTL work, it finally simulates correctly, and you’re ready to go to synthesis and place-and-route. It should be smooth sailing from here.

The first run through synthesis (after you got rid of all the non-synthesizable constructs and entered all those timing constraints) looks like not-so-bad news. You have three paths not meeting timing, all with minimal negative slack. We’ll call them A, B, and C. Since they’re within 5% of the constraint, you figure you’ll just dash on into place-and-route and see what happens. (You read our “synthesis shootout” article and know not to put too much stock in pre-layout timing estimates anyway).

Your first hint that it might be a bad day comes when place-and-route is still running as you leave your desk for lunch. You’d hoped it would be done so you could look at the results before you took your break. The plot begins to thicken when you come back from lunch and place-and-route is still chugging away. You double-check the process monitor and see that your machine is apparently fine. The tool is just running longer than expected. You stay an extra hour after work to see if it completes by the end of the day, and then leave, a little concerned that there might be a problem. [more]